Abstract: In this work, hydrogenated amorphous silicon thin film transistors (-Si:H TFTs) with the 98 nm thick nano -Si:H thin film and the channel aspect ratio 10 m/40 m are demonstrated, which are based on silicon-on-insulator (SOI) materials and fabricated by RF-PECVD system. The methods, SEM, XRD as well as Raman spectra, are employed to characterize the morphologic and structural properties of the nano -Si:H thin film at different annealing temperatures. CMOS processing, anisotropic etching solution EPW, radio frequency spurting and plasma etching techniques are adopted to fabricate -Si:H TFTs together with IDS-VDS characteristics. Besides ubiquitous characteristics of -Si:H TFTs, the simulation model, allowing for energy balance transport mechanism, is established to specially investigate negative resistance phenomena occurred during experiments. The results from the extraction of the energy band diagram at the interface between the nano -Si:H thin film and gate oxide indicate that the valence band energy decreases with the drain voltage ascending from 6 V to 30 V adjacent to the drain within 0.5 m. All these demonstrate that the fallen voltage close to the drain within 0.5 m is responsible for the negative resistance characteristics.