基于TLP建模的系统级静电放电效应仿真

陈强; 徐可; 陈真真; 陈星

doi:10.11884/HPLPB201931.190113

基于TLP建模的系统级静电放电效应仿真

doi: 10.11884/HPLPB201931.190113

四川大学电子信息学院, 成都 610065

基金项目:

四川大学研究生创新基金项目 2018YJSY061

详细信息

作者简介:
陈强(1992-), 男，博士研究生，主要从事天线设计，多物理场仿真方面的研究；dennie_chen@163.com

中图分类号: TN701
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出版历程
- 收稿日期: 2019-04-17
- 修回日期: 2019-05-16
- 刊出日期: 2019-10-15

System-level electrostatic discharge simulation based on transmission line pulse modeling

School of Electronics and Information Engineering, Sichuan University, Chengdu 610065, China

摘要

摘要: 系统级静电放电(ESD)效应仿真可以在电子系统进行测试之前进行有效的静电放电效应防护，缩短研发周期。根据传输线脉冲测试(TLP)结果，对瞬态电压抑制(TVS)二极管和芯片引脚进行spice行为建模，结合ESD脉冲源的等效电路模型，PCB板的S参数模型，采用场路协同技术完成了系统级静电放电效应的仿真。针对一个典型的电子系统，在IEC 61000-4-2 ESD应力作用下，完成了一款开关芯片防护电路的仿真，并对电路进行了加工、放电测试，仿真与测试芯片引脚的电压波形吻合良好，验证了该仿真方法的有效性。
- 静电放电 /
- 传输线脉冲测试 /
- TVS二极管 /
- spice模型 /
- 场路协同仿真
Abstract: Effective protection can be conducted before an electronic system is measured through system-level ESD simulation. In this paper, the spice behavioral modeling for the transient voltage suppressor and IC pins are presented using the measured transmission line pulse (TLP) data. A system-level ESD simulation methodology is proposed, including the equivalent circuit model of ESD pulse source, S-parameter model of PCB board, TLP model of TVS protection diode, IC pins and co-simulation technology. A switch chip protect circuit is simulated and measured under IEC 61000-4-2 ESD stress. The good agreement between simulated and measured voltage waveforms demonstrates the effectiveness of the proposed simulation method.
- electrostatic discharge /
- TLP /
- TVS diode /
- spice model /
- field-circuit co-simulation

HTML全文

图 1 系统级ESD仿真的构型

Figure 1. Modeling components needed in system-level ESD simulation

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图 2 ESD脉冲等效电路及放电波形

Figure 2. ESD waveform and its equivalent circuit

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图 3 TVS二极管和芯片的TLP数据

Figure 3. TLP data for TVS and chip pins

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图 4 ESD作用的电子系统

Figure 4. Electronic system under ESD stress

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图 5 ESD测试电路板

Figure 5. Fabricated circuit board for ESD measurement

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图 6 芯片端口的电压波形(只加载开关芯片)

Figure 6. Voltage waveform of chip port (with only switch chip loaded)

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图 7 芯片端口的电压波形(加载有回滞特TVS二极管和开关芯片)

Figure 7. Voltage waveform of chip port (load TVS diode with snapback and switch chip)

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图 8 芯片端口的电压波形(加载无回滞特性TVS二极管和开关芯片)

Figure 8. Voltage waveform of chip port (load TVS diode with snapback and switch chip)

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表 1 IEC规定的ESD波形参数

Table 1. IEC defined ESD waveform parameters

level	indicated voltage/kV	first peak current of discharge ±10%/A	rise time with discharge switch/ns	current (±10%) at 30 ns/A	current (±10%) at 6 ns/A
1	2	7.5	0.7~1	4	2
2	4	15	0.7~1	8	4
3	6	22.5	0.7~1	12	6
4	8	30	0.7~1	16	8

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参考文献(11)

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