PCIe electromagnetic interference analysis and optimization design based on co-simulation of field and circuit
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摘要: 采用电磁仿真技术，提前评估PCB的电磁兼容设计是否合理，当对PCB进行电磁兼容测试时，减少其电磁干扰不满足GMW 3097标准的情况出现。首先对PCB进行3D电磁场仿真，再与高速串行计算机扩展总线标准模块内芯片的通用模拟电路仿真模型的电路仿真动态链接，进行场路协同仿真。实验验证表明，该仿真方法的精度在6 dBμV之内，满足PCB加工工艺的误差和实验测试的不确定度，符合仿真精度要求。通过该仿真方法评估PCB的电磁干扰强度以及优化PCB的设计，将高速串行计算机扩展总线标准模块上的33 Ω电阻替换为磁珠后，该PCB在1.6 GHz处的电磁干扰强度降低了13.4 dB。根据CISPR 25标准规定的1-m法进行测试，PCB的电磁干扰变为−3.4 dBμV，低于GMW 3097标准要求，从而验证了该措施的有效性。
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关键词:
- PCIe模块 /
- 共模辐射 /
- 电磁干扰 /
- 通用模拟电路仿真模型 /
- 电磁仿真
Abstract: In this paper, the rationality of Electromagnetic Compatibility（EMC）design of Printed Circuit Board (PCB) is evaluated in advance through electromagnetic simulation. The purpose of this method is to reduce the chances that the Electromagnetic Interference (EMI) of PCB does not meet GMW 3097 standard in EMC test. Firstly, the 3D electromagnetic field simulation of the Peripheral Component Interconnect express (PCIe) module on the PCB is performed. Then the field simulation is dynamically linked with the circuit simulation of the Simulation Program with Integrated Circuit Emphasis (SPICE) model of chip on the PCIe module, so that the co-simulation of field and circuit is performed. According to the experimental test, the accuracy of this simulation method is within 6 dBμV, which satisfies the deviation of PCB processing technology and the uncertainty of the experimental test. Thus, this simulation method meets the accuracy requirements. Therefore, the EMI of PCB can be evaluated and the PCB design can be optimized by this simulation method. After the 33 Ω resistors on the PCIe module was replaced by magnetic beads, the EMI of the PCB at 1.6 GHz is reduced by 13.4 dB. According to the 1-m method specified in the CISPR 25 standard for testing, the EMI of PCB becomes −3.4 dBμV, which is lower than the GMW 3097 standard requirement. Therefore, the effectiveness of this measure is verified. -
图 2 PCB上电流驱动信号传输示意图
Figure 2. Schematic diagram of current drive signal transmission on PCB
图 3 PCIe模块上的时钟的时域信号示意图
Figure 3. Schematic diagram of the time domain signals of the clock on the PCIe module
图 4 PCIe模块上的时钟的频域信号示意图
Figure 4. Schematic diagram of the frequency domain signal of the clock on the PCIe module
图 5 自由空间中的无限小电偶极子的辐射
Figure 5. Radiation of an infinitesimal electric dipole in free space
图 7 PCIe模块的仿真数据与实验数据对比图
Figure 7. Comparison of simulation data and experimental data of PCIe module
表 1 GMW 3097标准中对EMI的要求
Table 1. The EMI requirements for the GMW 3097 standard
name frequency/MHz EMI limit GPS 1 567 − 1 574 linearly decreased from 44 dBμV to 4 dBμV 1 574 − 1 576 4 dBμV 1 576 − 1 583 linearly increased from 4 dBμV to 44 dBμV GLONASS 1 598 − 1 606 4 dBμV 
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