Design and implementation of digital delay and pulse generator of BEPC II linear accelerator
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摘要: 针对北京正负电子对撞机II期（BEPC II）直线加速器升级改造过程中束流位置探测器（BPM）电子学对外部触发信号的需求，设计了一台高精度延时控制、上升时间短和参数灵活调节的数字延时触发器。采用FPGA（现场可编程门阵列）作为主控制器展开设计，重点介绍了基于FPGA的边沿检测模块和多通道延时处理模块的设计与仿真，描述了FPGA和驱动电路的设计方案以及在直线加速器上的应用。经测试，延时可调范围4 ns～4 μs，最小步进4 ns，步进误差0.125%；上升时间2 ns，延时抖动135.4 ps。Abstract: A digital delay and pulse generator with high precision delay control, short rise time and flexible parameter adjustment is designed to meet the needs of BPM electronics for external trigger signals in the process of upgrading the BEPC II linear accelerator. An FPGA is used as the main controller. This paper mainly introduces the design principle and simulation results of edge detection module and multi-channel delay processing module based on FPGA software platform, and describes the design of FPGA and drive circuit, and its application in linear accelerator. The test results show that the output pulse of the digital delay generator has an adjustable delay range of 4 ns～4 μs, a minimum step of 4 ns, an adjustable error of 0.125%, a rise time of 2 ns, and a delay jitter of 135.4 ps.
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Key words:
- linear accelerator /
- FPGA /
- adjustable delay /
- rise time /
- multiple fan-out /
- driver circuit
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图 4 边沿检测模块行为级仿真波形图
Figure 4. Behavior level simulation waveform of edge detection module
图 6 多通道延迟处理模块行为级仿真波形图
Figure 6. Behavior level simulation waveform of multichannel delay processing module
图 10 数字延时触发器实验平台
Figure 10. Experimental platform of digital delay and pulse generator
图 12 BEPC II直线加速器现场运行图
Figure 12. Operation diagram of BEPC II linear accelerator’s BPM electronics and the delay generator
图 13 数字延时触发器与束流信号测试波形图
Figure 13. Test waveforms of digital delay and pulse generator and beam signal
表 1 数字延时触发器的参数需求
Table 1. Parameter requirements for digital delay and pulse generator
pulse width/μs fixed delay/μs range of adjustable delay/ns minimum step/ns rise time/ns output channels output voltage/V 5 1.3 4～1 000 4 ＜16 10 5 
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