Damage characteristics and physical mechanism of the CMOS inverter under fast-rising-edge electromagnetic pulse
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摘要:
随着电磁环境的日益复杂，保证集成电路（IC）的可靠性成为一个巨大的挑战。在此基础上，通过对CMOS反相器的仿真和实验研究，研究了快上升沿电磁脉冲（EMP）引起的陷阱辅助隧穿（TAT）效应。对此进行了详细的机理分析用于解释其物理损伤过程。EMP感应电场在氧化层中产生陷阱和泄漏电流，从而导致器件的输出退化和热失效。建立了退化和失效的理论模型，以描述输出退化及热积累对EMP特征的依赖性。温度分布函数由半导体中的热传导方程导出。基于TLP测试系统进行的相应实验证实了出现的性能退化，与机理分析一致。Sentaurus TCAD的仿真结果表明，EMP引起的损坏是由栅极氧化层中发生的TAT电流路径引起的，这也是器件的易烧坏位置。此外，还讨论了器件失效与脉冲上升沿的关系。本文的机理分析有助于加强其他半导体器件的EMP可靠性研究，可以对CMOS数字集成电路的EMP加固提出建议。
Abstract:Ensuring the reliability of integrated circuits (ICs) has been a great challenge with the increasing complexity of the electromagnetic environment. On this basis, the fast-rising-edge electromagnetic pulse (EMP)-induced trap-assisted tunneling (TAT) effect is investigated by simulation and experiments of CMOS digital inverters. A detailed mechanism analysis is performed to explain the physical damage process. The EMP-induced field derives traps and leakage current in the oxide, which induces output degradation and thermal failure in the device. A theoretical model of degradation and failure is established to describe the dependency of the output deterioration and the heat accumulation on the EMP resulting signal features. The temperature distribution function is derived from the heat conduction equation in the semiconductor. Corresponding experiments performed based on the TLP test system substantiate the emerging performance deterioration, which is in agreement with the mechanism analysis. Simulated results from the Sentaurus TCAD indicate that EMP resulting voltage-induced damage is caused by the TAT current path occurring in the gate oxide, revealing the location susceptible to burnout. In addition, the dependency of the device failure on the pulse rising time is discussed. The mechanism analysis in this paper facilitates reinforcing the design and promotes EMP reliability research on other semiconductor devices, and the study contributes to the enhancement of EMP robustness in CMOS digital ICs.
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Key words:
- CMOS inverter /
- electromagnetic pulse /
- trap-assisted tunneling /
- mechanism analysis
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Figure 3. Schematic of the fast-rising-edge EMP resulting voltage signal experiment based on the TLP testing system
Figure 4. Injection experiments of EMP resulting voltage signal with fast rising edges
Figure 5. Typical TLP current-voltage characteristic curve and reverse leakage current curve of type A sample
Figure 8. Simulated current density under EMP resulting voltage signal. Detailed current distribution of the NMOS region under (a) 0 V, (c) 5 kV, and (e) 10 kV. The corresponding current of the PMOS region is shown in (b), (d) and (f)
Figure 9. Lattice temperature of the CMOS inverters under EMP resulting voltage signal
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