High-speed parallel equalization algorithm and its FPGA implementation in THz communication
-
摘要: 基于驰豫超前变换中的超前展开、求和近似和延时近似技术，提出了流水线并行自适应CMA盲均衡算法。利用基于迭代短卷积的并行FIR滤波算法分析了提出的并行自适应盲均衡算法的滤波部分的高效实现结构；再利用基于组合短卷积的并行自适应系数更新算法分析了提出的并行均衡算法的系数更新部分的高效实现结构，从而得到了基于短卷积的流水线并行自适应盲均衡的完整实现框图，并分析了各模块的流水线延时需满足的关系。最后对该并行自适应盲均衡算法进行了FPGA量化实现，并通过MATLAB仿真及实际FPGA实现结果的对比，验证了本并行均衡算法的正确性和有效性。Abstract: Using look-ahead unwrap, sum relaxation and delay relaxation of relaxed look-ahead technique, we develop a pipelined parallel adaptive CMA blind equalization algorithm. An iterated short convolution based fast parallel FIR filter is used to analyze the implementation structure of the filter part of the proposed parallel adaptive equalizer. Meanwhile, a combined short convolution based parallel adaptive weight update algorithm is used to analyze the implementation structure of the weight update part of the proposed parallel adaptive equalizer. A short convolution based, effective pipelined parallel implementation structure of adaptive CMA blind equalization algorithm is then obtained, and the required relationship of pipelined delays of different modules is achieved. FPGA implementation and simulations of the proposed algorithm are also conducted, and compared with MATLAB simulation.
-
点击查看大图
计量
- 文章访问数: 1520
- HTML全文浏览量: 232
- PDF下载量: 331
- 被引次数: 0
下载:
