Design of synchronous controller for accelerator based on FPGA
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摘要: 针对加速器驱动次临界系统（ADS）注入器Ⅱ的控制中对于同步触发信号的要求，设计了基于现场可编程门阵列（FPGA）的高精度同步控制器，它能为加速器设备提供同步工作所需的脉冲信号。控制器采用粗延时结合精延时的方式，FPGA实现粗延时，专用延时芯片实现精延时，提高了延时精度，同时增大了延时、脉宽及周期的调节范围。测试结果表明，该控制器输出脉冲的最小延时步距为0.25 ns，延时、脉宽及周期调节范围为1 s~2 s，周期抖动的标准偏差为70 ps。该控制器输出信号满足要求，程序界面操作简便，通过串口RS-422远程控制稳定可靠。
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关键词:
- 加速器驱动次临界系统 /
- 现场可编程门阵列 /
- 同步 /
- 脉冲 /
- 延时
Abstract: A synchronous controller based on FPGA is designed to meet the requirements in the process of controlling injector Ⅱ of accelerator driven sub-critical system (ADS). It provides 4 synchronous pulse signals for some equipments in injector Ⅱ. The controller combines coarse delay based on FPGA and fine delay based on dedicated delay chip to improve the precision of delay and increase the adjustable ranges of period, pulse width and delay. The delay per step is 0.25 ns. Delay, period and pulse width range from 1 s to 2 s. The standard deviation of period jitter is 70 ps. The output signals meet the specified requirements. The program of this controller is easy to operate, and the remote control is stable and reliable. -
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