四级串联共用腔体MA级FLTD的设计与仿真

孙凤举; 姜晓峰; 王志国; 魏浩; 邱爱慈

doi:10.11884/HPLPB201830.170351

四级串联共用腔体MA级FLTD的设计与仿真

doi: 10.11884/HPLPB201830.170351

西北核技术研究所, 强脉冲辐射模拟与效应国家重点实验室, 西安 710024

基金项目:

国家自然科学基金项目 5179520012

国家自然科学基金项目 51790521

国家自然科学基金项目 51790523

详细信息

作者简介:
孙凤举(1967—)，男，博士，研究员，主要从事脉冲功率技术研究; sun-feng-ju@126.com

中图分类号: TL51;TM836
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出版历程
- 收稿日期: 2017-09-04
- 修回日期: 2017-11-09
- 刊出日期: 2018-03-15

Design and simulation of fast linear transformer driver with four stages in series sharing common cavity shell and mega-ampere current

State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology, P. O. Box 69-10, Xi'an 710024, China

摘要

摘要: 目前MA级快脉冲直线变压器驱动源(FLTD)模块一般引入2~4路快前沿(约20 ns)高幅值(100 kV)电脉冲触发，百TW级数十MA的FLTD驱动源含有数千个模块，其触发系统非常庞大，并且要求触发脉冲按照精确时序到达各级串联模块，以便实现与次级行波同步的感应电压高效叠加，触发系统成为大型FLTD驱动源的瓶颈之一。在之前提出的一种利用一路外触发脉冲实现数十模块串联FLTD与次级行波同步的感应电压高效叠加触发方式基础上，设计了4级串联共用腔体的MA级FLTD模块组，每级共24支路，其中1个用作触发支路，主放电支路由2只100 nF双端引出电极电容器和1只GW级气体开关组成；建立了16级串联、次级为水线的单路FLTD电路模型，数值仿真研究了支路开关自放电、触发支路开关闭合时序与分散性，以及次级传输线阻抗对驱动源的影响。
- 快Z箍缩 /
- FLTD驱动源 /
- 感应腔 /
- GW级气体开关 /
- 同步触发 /
- 触发时序
Abstract: Fast Linear Transformer Drivers (FLTDs) can directly produce high-power pulse with the rise time 70-200 ns, which are based on magnetic coupling by many bricks connected in parallel in a circular annulus to output MA current and tens of cavities connected in series to output MV voltage. FLTDs are regarded as the next petawatt drivers for Z-pinch by international scientific community. At present, mega-ampere scale FLTD cavities need two or four triggering pulses with 100 kV and rise time of 25 ns in general, so the petawatt FLTD drivers consist of several thousand cavities require ten thousands of the triggering pulses and should be arrived the different position cavities at accurate sequences in order to realize the secondary pulses to superpose inductively and efficiently, which is the bottleneck of the FLTD development. The paper presents a creative FLTD module with four stages in series sharing induction cavity shell and a novel trigger method achieving nearly ideal IVA triggering sequence for each FLTD module. The FLTD module with mega-ampere current output consisting of 16-cavities in series is designed. The circuit model of the new structure of 16-stage FLTD is developed. The influences of the switches' prefire of main bricks, the triggering brick switches' closing sequences and jitter, and the secondary transmission line impedances are simulated based on the circuit model.
- fast Z-pinch /
- fast linear transformer driver /
- cavities /
- GW gas spark switches /
- triggering synchronization /
- inductive voltage adder sequences

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图 1 主放电支路

Figure 1. Main brick of Fast Linear Transformer Driver (FLTD)

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图 2 主放电支路短路放电电流波形

Figure 2. Discharge current of main brick at short load

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图 3 四级串联共用腔体FLTD模块结构

Figure 3. Configuration of FLTD module with 4 stages sharing common cavity

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图 4 每级FLTD主放电支路触发连线方式

Figure 4. Line connection of triggering of switches

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图 5 16级串联FLTD等效电路模型

Figure 5. Equivalent circuit of 16-stage FLTD

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图 6 次级水传输线电路模型

Figure 6. Model of secondary water-insulated transmission line

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图 7 匹配负载电流随支路电感的变化

Figure 7. Load current waveforms

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图 8 支路开关自放电其他支路开关两端电压的变化

Figure 8. Voltages of other switches when one switch prefires, impedance coefficient m=1 to 5

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图 9 自放电支路电流m=1~5

Figure 9. Current of prefire brick, m=1 to 5

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图 10 自放电支路和正常放电时支路电流波形

Figure 10. Prefire brick current and normal operating brick's current

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图 11 采用IVA时序开关闭合时间分散性对16级串联FLTD负载电流波形的影响

Figure 11. Influence of time jitters of closing sequence of FLTD switches at ideal IVA mode on matched impedance load current

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图 12 三种典型时序下匹配负载波形

Figure 12. Load current at three triggering sequences

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图 13 α从0到3，间隔0.15负载电流波形

Figure 13. Load currents when triggering coefficient α from 0 to 3 interval 0.15

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表 1 负载电流峰值与前沿随支路电感的变化

Table 1. Load's peak current and rise time change with brick inductance

L_b/nH	I_p/kA	T_r/ns	L_b/nH	I_p/kA	T_r/ns
140	992	46.8	150	963	48.4
160	936	50.6	170	912	52.7
180	889	54.9	190	868	57.1
200	847	59.1	210	830	61.3
220	812	63.5	230	797	65.4
240	781	67.4	250	766	69.4
260	753	71.1

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表 2 开关闭合分散性对负载电流峰值及前沿的影响

Table 2. Influence of time jitters of closing sequence of FLTD switches on load current peak and rise time

Δt/ns	I_p/kA				rise time (0.1~0.9): T_r/ns
Δt/ns	max	min	average	δ	max	min	average	δ
3	868	836	849	5.9	70	58	62	2.8
5	867	831	849	8.4	75	55	65.5	4.6
10	899	828	861	16.1	103.5	58.7	74.0	8.8

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