留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

A 2 G/s sampling rate, 20 GHz bandwidth master-slave track-and-hold amplifier in 0.13 μm SiGe BiCMOS technology

Zhang Guifu Zhou Jie Liu Youjiang

张贵福, 周劼, 刘友江. 一款2 G/s采样率20 GHz带宽主从式跟踪保持电路设计研究[J]. 强激光与粒子束, 2020, 32: 063006. doi: 10.11884/HPLPB202032.190421
引用本文: 张贵福, 周劼, 刘友江. 一款2 G/s采样率20 GHz带宽主从式跟踪保持电路设计研究[J]. 强激光与粒子束, 2020, 32: 063006. doi: 10.11884/HPLPB202032.190421
Zhang Guifu, Zhou Jie, Liu Youjiang. A 2 G/s sampling rate, 20 GHz bandwidth master-slave track-and-hold amplifier in 0.13 μm SiGe BiCMOS technology[J]. High Power Laser and Particle Beams, 2020, 32: 063006. doi: 10.11884/HPLPB202032.190421
Citation: Zhang Guifu, Zhou Jie, Liu Youjiang. A 2 G/s sampling rate, 20 GHz bandwidth master-slave track-and-hold amplifier in 0.13 μm SiGe BiCMOS technology[J]. High Power Laser and Particle Beams, 2020, 32: 063006. doi: 10.11884/HPLPB202032.190421

一款2 G/s采样率20 GHz带宽主从式跟踪保持电路设计研究

doi: 10.11884/HPLPB202032.190421
详细信息
  • 中图分类号: TN242

A 2 G/s sampling rate, 20 GHz bandwidth master-slave track-and-hold amplifier in 0.13 μm SiGe BiCMOS technology

More Information
    Author Bio:

    Zhang Guifu (1977—), male, PhD candidate, engaged in sampling system construction and analog circuits design of high-speed sampling system; 18780430610@163.com

  • 摘要: 设计了一款全差分、20 GHz带宽主从式跟踪保持芯片(MS-THA)。该芯片采样率为2 G/s,工作带宽大于20 GHz,采用0.13 μm SiGe BiCMOS工艺实现。该芯片采用传统的开关发射极跟随器(SEF)作为跟踪保持核心电路,Cherryhooper电路作为输入缓冲和输出缓冲的带宽增强核心电路,并利用交叉反馈电容抑制馈通。为了验证上述电路的有效性,设计了一个单级THA电路,测试结果为MS-THA电路提供了足够的支持。在单电源+3.3 V供电、输入直流电平为0 V,2 G/s采样率以及−3 dBm输入信号功率条件下,获得的单端输出无杂散动态范围小于−23.5 dB,总功耗约为300 mW。
  • Figure  1.  Block architecture of a simple core THA

    Figure  2.  Block architecture of the fabricated MS-THA

    Figure  3.  Microphotographs of the THAs: (a) circuit of the test-THA (1.3 mm×1.05 mm) and (b) MS-THA (2.0 mm× 1.05 mm) with bias voltage Vcc=3.3 V, power consumption 300 mW

    Figure  4.  Schematic of sampling clock buffer

    Figure  5.  Schematics of input and output buffers

    Figure  6.  Schematics of master and slave T/H core circuits

    Figure  7.  Device (chip inside) under test (DUT)

    Figure  8.  General test set-up configuration for both test-THA and MS-THA

    Figure  9.  Input and output return loss test results of the test-THA and the MS-THA

    Figure  10.  Single-ended sampling bandwidth test results of the test-THA and the MS-THA

    Figure  11.  Single-ended output spurious level test results of MS-THA

    Figure  12.  Output noise level test results without input signal

    Figure  13.  Typical output track-and-hold waveforms

    Table  1.   Results of experiments of the MS-THA chip

    architecture sampling
    rate/(G/s)
    input
    range/mV
    BW/GHz
    spurious free
    dynamic range/dBc
    supply
    voltage/V
    power
    consumption/W
    output
    noise/mV
    chip size process
    1 input,
    1 output
    2 450 ~20 (−2 dB)
    in switched phase
    <−23.5 dBc
    (single-ended)
    3.3 0.3 0.5 2.00 mm×
    1.05 mm
    0.13 μm SiGe BiCMOS
    (ft=250 GHz)
    下载: 导出CSV

    Table  2.   Performance comparison with similar bandwidth chips

    sourcesampling rate/(G/s)input/output dynamic/(mVpp)BW/GHzSFDR or THD/dBcdie-size/
    (mm×mm)
    supply/Vpower/Wprocess ft/GHz
    Ref. [14]501 80027−29.5@15 GHz0.94−5, −2.51.2InP DHBT/370
    Ref. [15]205009.9−45@0.9 GHz
    ~18@9.9 GHz
    4−5.20.74InP HBT/175
    Ref. [16]4050027−48 type−61.9InP /210
    Ref. [18]501 000/62525a−36.5@25 GHz1.8−6.21.85InP /300
    Ref. [21]80~70022−32.9@19.9 GHz0.35~1.2~0.532 nm SOI CMOS
    Ref. [24]8~400@1.1 GHz20−38.7@12 GHz0.6720.23665 nm CMOS
    Ref. [25]30164622.20.50.15 μm GaAs
    Ref. [26]1060038b−55.8@1 GHz0.07−50.5860.13 μm SiGe
    this work 2 450>20<−23.5(single-ended)2.13.30.30.13 μm SiGe
    Note: (a) 25 GHz is the highest test frequency in switched phase; (b) 38 GHz is the bandwidth of output buffer.
    下载: 导出CSV
  • [1] Lee J, Baeyens Y, Weiner J, et al. A 50 GS/s distributed T/H amplifier in 0.18 μm SiGe BiCMOS[J]. IEEE ISSCC Dig Tech Papers, 2007: 466-616.
    [2] Lu Y, Kuo W M L, Li X, et al. An 8-bit, 12 GSample/sec SiGe track-and-hold amplifier[C]//Proc IEEE BCTM, 2005: 148-151.
    [3] Jensen J C, Larson L E. A broadband 10-GHz track-and-hold in Si/SiGe HBT technology[J]. IEEE J Solid-State Circuits, 2001, 36(3): 325-330. doi: 10.1109/4.910470
    [4] Cheng W, Ali W, Choi M J, et al. A 3 b 40 GS/s ADC-DAC in 0.12 μm SiGe[J]. IEEE ISSCC Dig Tech Papers, 2004: 262-263.
    [5] Shahramian S, Chan Carusone A, Voinigescu S P. Design methodology for a 40-GSamples/s track and hold amplifier in 0.18 μm SiGe BiCMOS technology[J]. IEEE J Solid-State Circuits, 2006, 41(10): 2233-2240. doi: 10.1109/JSSC.2006.878111
    [6] Li X, Kuo W L, Lu Y, et al. A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier[C]//Proc IEEE CSICS, 2005: 105-108.
    [7] Borokhovych Y, Gustat H, Tillack B, et al. A low-power, 10 GS/s track-and-hold amplifier in SiGe BiCMOS technology[C]//Proc 31st IEEE ESSCIRC, 2005: 263-266.
    [8] Shahramian S, Chan Carusone A, Voinigescu S P, et al. A 40-G samples/sec track & hold amplifier in 0.18 m SiGe BiCMOS technology[C]//Proc IEEE CSICS, 2005: 101-104.
    [9] Haider S, Osmany S A, Gustat H, et al. A 10 GS/s 2 emitter follower only track and hold amplifier in SiGe BiCMOS technology[C]//Proc IEEE ISCAS, 2006: 4775-4778.
    [10] Halder S, Gustat H, Scheytt C. An 8 bit 10 GS/s 2 track and hold amplifier in SiGe BiCMOS technology[C]//Proc 32nd IEEE ESSCIRC, 2006: 416-419.
    [11] Li X, Kuo W M L, CresslerJ D. A 40 GS/s SiGe track-and-hold amplifier[C]//Proc IEEE BCTM, 2008: 1-4.
    [12] Shahramian S, Voinigescu S P, Carusone A C. A 30-GS/sec track and hold amplifier in 0.13-μm CMOS technology[C]//Proc IEEE CICC, 2006: 493-496.
    [13] Bouvier Y, Konczykowska A, Ouslimani A, et al. A 20-GSamples/s track-hold amplifier in InP DHBT technology[C]//Proc IEEE EuMIC, 2007: 1-4.
    [14] Daneshgar S, Griffith Z, Seo M, et al. Low distortion 50 GSamples/s track-hold and sample-hold amplifiers[J]. IEEE J Solid-state Circuits, 2014, 49(10): 2114-2126. doi: 10.1109/JSSC.2014.2329843
    [15] Yamanaka S, Sano K, Murata K. A 20-Gs/s track-and-hold amplifier in InP HBT technology[J]. IEEE Trans Microw Theory Tech, 2010, 58(9): 2334-2339. doi: 10.1109/TMTT.2010.2057174
    [16] Bouvier Y, Ouslimani A, Konczykowska A, et al. A 40 Gsamples/s InP-DHBT track-&-hold amplifier[C]//Proc IEEE EuMIC, 2010: 61-64.
    [17] Lee J, Leven A, Weiner J S, et al. A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology[J]. IEEE J Solid-State Circuits, 2003, 38(9): 1533-1539. doi: 10.1109/JSSC.2003.815926
    [18] Deza J, Ouslimani A, Konczykowska A, et al. A 50-GHz-small-signal-bandwidth 50 GSa/s track&hold amplifier in InP DHBT technology[C]//Proc IEEE MTT-S Int Microwave Symp, 2012: 1-3.
    [19] Deza J, Ouslimani A, Konczykowska A, et al. 70 GSa/s and 51 GHz bandwidth track-and-hold amplifier in InP DHBT process[J]. Electron Lett, 2013, 49(6): 388-389. doi: 10.1049/el.2013.0271
    [20] Gathman T D, Madsen K N, Li J C, et al. A 30 GS/s double-switching track-and-hold amplifier with 19 dBm IIP3 in an InP BiCMOS technology[J]. IEEE ISSCC Dig Tech Papers, 2014: 1-3.
    [21] Kull L, Toifl T, Schmatz M, et al. 22.1 A 90 GS/s 8b 667 mW 64× Interleaved SAR ADC in 32 nm Digital SOI CMOS[C]//IEEE International Solid-State Circuits Conference, 2014.
    [22] Daneshgar S, Griffith Z, Rodwell M J W. A high IIP3, 50 GSamples/s track and hold amplifier in 0.25 m InP HBT technology[C]//Proc IEEE CSICS, 2012: 1-4.
    [23] Lin Yu-An, Ya-Che Yeh, Yu-Cheng Liu, et al. A 55-dB SFDR 16-GS/s track-and-hold amplifier in 0.18 μm SiGe using differential feedthrough cancellation technique[C]//IEEE MTT-S Int Microwave Symp, 2016.
    [24] Na Yunsik Mehmood, Zubair Kang, Sungbin Jung, et al. an 8 GS/s 20 GHz bandwidth master-slave track-and-hold amplifier in 65 nm CMOS[J]. Microwave and Optical Technology Letters, 2018, 60(12): 3080-3084. doi: 10.1002/mop.31412
    [25] Lin Y A, Hong-Yeh Chang, Yu-Chi Wang, et al. DC-16 GHz GaAs track-and-hold amplifier using sampling rate and linearity enhancement techniques[J]. Electronics Letters, 2018, 54(2): 83-85. doi: 10.1049/el.2017.3372
    [26] Shen Yu, Yi Zhang, Lei Yang, et al. A 10 GS/s 0.13 μm SiGe track-and-hold amplifier with 38 GHz analog bandwidth[C]//International Conference on Microwave and Millimeter Wave Technology, 2018.
  • 加载中
图(13) / 表(2)
计量
  • 文章访问数:  1545
  • HTML全文浏览量:  421
  • PDF下载量:  47
  • 被引次数: 0
出版历程
  • 收稿日期:  2019-11-05
  • 修回日期:  2020-03-10
  • 刊出日期:  2020-05-12

目录

    /

    返回文章
    返回