A 2 G/s sampling rate, 20 GHz bandwidth master-slave track-and-hold amplifier in 0.13 μm SiGe BiCMOS technology
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摘要: 设计了一款全差分、20 GHz带宽主从式跟踪保持芯片(MS-THA)。该芯片采样率为2 G/s,工作带宽大于20 GHz,采用0.13 μm SiGe BiCMOS工艺实现。该芯片采用传统的开关发射极跟随器(SEF)作为跟踪保持核心电路,Cherryhooper电路作为输入缓冲和输出缓冲的带宽增强核心电路,并利用交叉反馈电容抑制馈通。为了验证上述电路的有效性,设计了一个单级THA电路,测试结果为MS-THA电路提供了足够的支持。在单电源+3.3 V供电、输入直流电平为0 V,2 G/s采样率以及−3 dBm输入信号功率条件下,获得的单端输出无杂散动态范围小于−23.5 dB,总功耗约为300 mW。
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关键词:
- 主从式 /
- 跟踪保持放大器 /
- SiGe BiCMOS工艺 /
- 无杂散动态范围
Abstract: A fully-differential master-slave track-and-hold amplifier (MS-THA), with 20 GHz bandwidth is designed and fabricated using 0.13 μm SiGe BiCMOS technology. The MS-THA employs conventional switched-emitter-follower (SEF) as track-and-hold core circuit, Cherryhooper circuits as band-boosting of input buffer and output buffer. To verify the validity of the above circuits, a single-stage THA is designed together with the MS-THA. Operating with a single +3.3 V supply, 0 V input direct-voltage, 2 G/s sampling and −3 dBm input power, the MS-THA achieves a single-ended spurious free dynamic range (SFDR) of less than −23.5 dB at frequency of up to 20 GHz, and total power consumption of about 300 mW.-
Key words:
- master-slave /
- track-and-hold amplifier /
- SiGe BiCMOS /
- spurious free dynamic range
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Table 1. Results of experiments of the MS-THA chip
architecture sampling
rate/(G/s)input
range/mVBW/GHz spurious free
dynamic range/dBcsupply
voltage/Vpower
consumption/Woutput
noise/mVchip size process 1 input,
1 output2 450 ~20 (−2 dB)
in switched phase<−23.5 dBc
(single-ended)3.3 0.3 0.5 2.00 mm×
1.05 mm0.13 μm SiGe BiCMOS
(ft=250 GHz)Table 2. Performance comparison with similar bandwidth chips
source sampling rate/(G/s) input/output dynamic/(mVpp) BW/GHz SFDR or THD/dBc die-size/
(mm×mm)supply/V power/W process ft/GHz Ref. [14] 50 1 800 27 −29.5@15 GHz 0.94 −5, −2.5 1.2 InP DHBT/370 Ref. [15] 20 500 9.9 −45@0.9 GHz
~18@9.9 GHz4 −5.2 0.74 InP HBT/175 Ref. [16] 40 500 27 −48 type −6 1.9 InP /210 Ref. [18] 50 1 000/625 25a −36.5@25 GHz 1.8 −6.2 1.85 InP /300 Ref. [21] 80 ~700 22 −32.9@19.9 GHz 0.35 ~1.2 ~0.5 32 nm SOI CMOS Ref. [24] 8 ~400@1.1 GHz 20 −38.7@12 GHz 0.67 2 0.236 65 nm CMOS Ref. [25] 30 16 46 2 2.2 0.5 0.15 μm GaAs Ref. [26] 10 600 38b −55.8@1 GHz 0.07 −5 0.586 0.13 μm SiGe this work 2 450 >20 <−23.5(single-ended) 2.1 3.3 0.3 0.13 μm SiGe Note: (a) 25 GHz is the highest test frequency in switched phase; (b) 38 GHz is the bandwidth of output buffer. -
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