基于MTCA的HLS-II直线加速器低电平系统改造

任天祺; 唐雷雷; 周泽然

doi:10.11884/HPLPB202032.200080

基于MTCA的HLS-II直线加速器低电平系统改造

doi: 10.11884/HPLPB202032.200080

中国科学技术大学国家同步辐射实验室，合肥 230026

基金项目: 国家自然科学基金项目（11675170）

详细信息

作者简介:
任天祺（1995－），男，硕士，从事加速器低电平系统研究；rentian@mail.ustc.edu.cn

通讯作者:
周泽然（1982－），男，副研究员，从事加速器束测低电平研究；zhouzr@ustc.edu.cn

中图分类号: TL503.2
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出版历程
- 收稿日期: 2020-03-27
- 修回日期: 2020-06-05
- 刊出日期: 2020-08-13

Upgrade of low level RF system based on Micro Telecom Computing Architecture (MTCA) for HLS-II LINAC

National Synchrotron Radiation Laboratory, University of Science and Technology of China, Hefei 230026, China

摘要

摘要: 合肥光源（HLS-II）在重大维修改造之后，其光源性能有了很大的提升。为了进一步实现连续、平稳地供光，需要对其进行恒流改造。恒流运行要求直线加速器的微波功率源有长期的稳定性与可靠性，旧的模拟低电平控制系统满足不了要求。本文基于微型电信计算平台（MTCA）设计实现了数字低电平控制系统，控制微波功率源的幅度和相位，它由以FPGA为核心的数字板卡、射频板卡、MTCA机箱以及频率合成系统组成。该数字低电平系统工作在2856 MHz的S波段，在线运行幅度稳定度达到0.04%，相位稳定度达到0.2°，满足恒流改造对直线加速器数字低电平系统0.25°相位抖动RMS值的相位精度要求。
- 合肥光源 /
- 直线加速器 /
- 低电平系统 /
- FPGA /
- MTCA
Abstract: The performance of Hefei Light Source II (HLS-II) has improved a lot after major maintenance and reconstruction. To further provide continuous and stable light, the RF system of the HLS-II LINAC needs to be upgraded for top-off mode. It is required that the RF power source have long-time stability and reliability, but the old analog low level RF system(LLRF) can’t meet the requirement. Hence a digital low level RF control system based on Micro Telecom Computing Architecture(MTCA) is designed and implemented to control the amplitude and phase of the RF power source. This system is composed of digital board cards based on FPGA, RF board cards, MTCA chassis and a frequency synthesis system. It works at 2856 MHz of S band, with phase and amplitude stability up to 0.2° and 0.04% respectively, which meets the top-off mode requirement of 0.25° RMS phase jitter of the digital low-level RF system in the HLS-II LINAC.
- HLS-II /
- LINAC /
- low level RF system /
- FPGA /
- MTCA

HTML全文

图 1 合肥光源直线加速器布局图

Figure 1. Layout of the linear accelerator of Hefei Light Source Ⅱ (HLS-Ⅱ)

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图 2 频率合成示意图

Figure 2. Diagram of the frequency synthesis system

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图 3 数字低电平控制系统结构框图

Figure 3. Structure diagram of the low level RF system

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图 4 FPGA中的数据通路

Figure 4. Data path in FPGA

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图 5 控制环路

Figure 5. Control loop

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图 6 低电平系统测量得到幅度与相位值

Figure 6. Amplitude and phase detected by LLRF system

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参考文献(10)

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