Study and implementation of automatic gain calibration method for 4-channel digital beam position monitor
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摘要: 在现有硬件基础上，基于BPM测量准确度的需求，在自制的电子学FPGA芯片内，通过Verilog语言实现了一种数字BPM采样数据增益自动校准的设计。首先介绍了自动增益校准模块的系统总体设计；然后对模块的实现方法做了详细说明，设计并搭建了ADC数据自动增益校准测试平台以验证自动增益较准模块的功能；最后介绍了该设计在BPM通道标定中的应用。实验结果表明，该方法可以实现4通道增益一致，使ADC采样后的数据幅度相同，有效解决了由通道增益不一致引起的测量偏差，以及工程应用中ADC数据幅度校准工作量大且难于操作的问题，将在BPM系统通道自动标定中发挥重要作用。Abstract: The accuracy of beam position measurement is affected by the gain inconsistency of the four channels of the digital BPM. Based on the existing hardware and the requirement of beam position monitor (BPM) measurement accuracy, a design for automatic calibration of digital BPM sample data gain is implemented by Verilog language in the self-made electronics. Firstly, the system design of automatic gain calibration module is introduced. Secondly, the realization method of the module is described in detail, and the ADC data automatic gain calibration test platform is designed and built to verify the function of the automatic gain calibration module. Finally, the application of this design in BPM channel calibration is introduced. Test results show that this method achieves 4-channel gain consistency and makes the data amplitude after ADC sampling equal. This method effectively solves the measurement bias caused by channel gain inconsistency and the difficulty of ADC data amplitude calibration in engineering application. It will play an important role in the automatic channel calibration of BPM system.
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Key words:
- digital beam position monitor /
- ADC sampling /
- FPGA /
- automatic gain calibration
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图 2 BPM数字采样处理电路结构框图
Figure 2. Structure diagram of BPM digital sampling and processing circuit
图 3 ADC采样数据自动增益校准原理框图
Figure 3. Block diagram of ADC sampling data automatic gain correction
图 5 ADC数据自动增益校准前数据示意图
Figure 5. Schematic diagram of ADC data before automatic gain calibration
图 6 ADC数据自动增益校准后数据示意图
Figure 6. Schematic diagram after ADC data automatic gain calibration
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