用于阵列天线连续跟踪的步进电机控制器IP核设计
Design of stepping motor control IP core for array antenna successive scanning
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摘要: 采用VHDL语言设计了一种基于现场可编程门阵列（FPGA）的步进电机控制器IP核，并在Quartus Ⅱ软件中进行了编译和仿真。该控制器采用了控制参数在线计算模块，使得阵列中每台步进电机都可以根据对应单元的相移量推算出各自的升降频曲线及脉冲发送时刻，从而保证阵列中各个电机的转动角度保持一定的关系，同时能有效地降低步进电机失步的风险。该控制器采用编码器反馈信息处理模块，对步进电机失步进行判断和校正。编译结果显示:通过合理设定数据位宽、重复利用乘法器、合理利用相邻脉冲发送间隔，控制器可以有效降低进行实时参数计算时的硬件资源使用量。测试结果表明，该控制器可以实现阵列天线波束连续跟踪。Abstract: This article uses VHDL to design a stepping motor control IP core based on FPGA which has been compiled and simulated in Quartus Ⅱ. This core calculates control parameters online, enabling every motor in the array to figure out its velocity profile and moments to send pulses in real time. At the same time, it can reduce the risk of losing steps. This IP core can handle the feedback signals from the encoder to judge and regulate step losses. The compilation result shows this IP core reduces the hardware resource consumed in real time calculation. The simulation result shows this IP core can achieve array antenna successive scanning.
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Key words:
- stepping motor /
- control ip core /
- successive scanning /
- array antenna
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