Design of synchronous controller for accelerator based on FPGA

Xu Weibin; Guo Yuhui; Zheng Yawei; Luo Bingfeng; Jia Huan

doi:10.11884/HPLPB201527.015101

Volume 27 Issue 01

Jan. 2015

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Article Navigation > High Power Laser and Particle Beams > 2015 > 27(01): 015101

Zhang Fan, Huang Xiuguang, Shu Hua, et al. Characteristics of dynamic fracture of aluminum and metallographic analysis of recovered samples in laser experiments[J]. High Power Laser and Particle Beams, 2015, 27: 071006. doi: 10.11884/HPLPB201527.071006

Citation:

Xu Weibin, Guo Yuhui, Zheng Yawei, et al. Design of synchronous controller for accelerator based on FPGA[J]. High Power Laser and Particle Beams, 2015, 27: 015101. doi: 10.11884/HPLPB201527.015101

Citation:

Xu Weibin, Guo Yuhui, Zheng Yawei, et al. Design of synchronous controller for accelerator based on FPGA[J]. High Power Laser and Particle Beams, 2015, 27: 015101. doi: 10.11884/HPLPB201527.015101

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Design of synchronous controller for accelerator based on FPGA

doi: 10.11884/HPLPB201527.015101

Xu Weibin^1,2,
Guo Yuhui^{1
,
,},
Zheng Yawei^1,2,
Luo Bingfeng^1,2,
Jia Huan^1,2

1.
Institute of Modern Physics,Chinese Academy of Sciences,Lanzhou 730000,China;
2.
University of Chinese Academy of Sciences,Beijing 100049,China

Received Date: 2014-06-05
Rev Recd Date: 2014-11-10
Publish Date: 2015-01-20

Abstract

Abstract

A synchronous controller based on FPGA is designed to meet the requirements in the process of controlling injector Ⅱ of accelerator driven sub-critical system (ADS). It provides 4 synchronous pulse signals for some equipments in injector Ⅱ. The controller combines coarse delay based on FPGA and fine delay based on dedicated delay chip to improve the precision of delay and increase the adjustable ranges of period, pulse width and delay. The delay per step is 0.25 ns. Delay, period and pulse width range from 1 s to 2 s. The standard deviation of period jitter is 70 ps. The output signals meet the specified requirements. The program of this controller is easy to operate, and the remote control is stable and reliable.
- accelerator driven sub-critical system,
- field programmable gate array (FPGA),
- synchronous,
- pulse,
- delay

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