Design and implementation of clock phaselocked circuit in digital beam position monitor

In order to realize the phase locking of the digital beam position monitor (BPM) clock system, a clock synchronization system with low jitter and low phase noise is designed based on the principle of PLL synchronization. According to the working principle of the PLL circuit, the hardware and firmware are designed for the digital BPM clock synchronization system, the phase locking of the external input clock signal and the systems internal main work clock signal is realized, the output frequency and phase of the clock signal can be adjusted to meet the ADC sampling requirements in the back-end. The test results show that the design can meet the phase locking for the external clock signal which changes in a certain frequency range and the output clock signal jitter satisfies the requirement of beam experiments. Meanwhile, this study provides a basis for the subsequent research of digital BPM.