High-speed parallel equalization algorithm and its FPGA implementation in THz communication

Lin Changxing; Deng Xianjin; Zhang Jian

doi:10.3788/HPLPB20132506.1587

Volume 25 Issue 06

Apr. 2013

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Article Navigation > High Power Laser and Particle Beams > 2013 > 25(06): 1587-1591

Chen Nan, Dai Man, Gao Feng, et al. Energy spectrum measurement with circular array method[J]. High Power Laser and Particle Beams, 2013, 25: 2995-2998. doi: 10.3788/HPLPB20132511.2995

Citation:

Lin Changxing, Deng Xianjin, Zhang Jian. High-speed parallel equalization algorithm and its FPGA implementation in THz communication[J]. High Power Laser and Particle Beams, 2013, 25: 1587-1591. doi: 10.3788/HPLPB20132506.1587

Chen Nan, Dai Man, Gao Feng, et al. Energy spectrum measurement with circular array method[J]. High Power Laser and Particle Beams, 2013, 25: 2995-2998. doi: 10.3788/HPLPB20132511.2995

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High-speed parallel equalization algorithm and its FPGA implementation in THz communication

doi: 10.3788/HPLPB20132506.1587

Lin Changxing^{1,2
,
,},
Deng Xianjin^1,2,
Zhang Jian^1,2

1.
Institute of Electronic Engineering,CAEP,P.O.Box 919-536,Mianyang 621900,China; 2.Terahertz Research Center,CAEP,P.O.Box 919-536,Mianyang 621900,China

Received Date: 2012-11-12
Rev Recd Date: 2012-12-10
Publish Date: 2013-04-08

Abstract

Abstract

Using look-ahead unwrap, sum relaxation and delay relaxation of relaxed look-ahead technique, we develop a pipelined parallel adaptive CMA blind equalization algorithm. An iterated short convolution based fast parallel FIR filter is used to analyze the implementation structure of the filter part of the proposed parallel adaptive equalizer. Meanwhile, a combined short convolution based parallel adaptive weight update algorithm is used to analyze the implementation structure of the weight update part of the proposed parallel adaptive equalizer. A short convolution based, effective pipelined parallel implementation structure of adaptive CMA blind equalization algorithm is then obtained, and the required relationship of pipelined delays of different modules is achieved. FPGA implementation and simulations of the proposed algorithm are also conducted, and compared with MATLAB simulation.
- parallel blind equalization,
- relaxed look-ahead transformation,
- short convolution,
- FPGA implementation

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