High-speed parallel equalization algorithm and its FPGA implementation in THz communication

Using look-ahead unwrap, sum relaxation and delay relaxation of relaxed look-ahead technique, we develop a pipelined parallel adaptive CMA blind equalization algorithm. An iterated short convolution based fast parallel FIR filter is used to analyze the implementation structure of the filter part of the proposed parallel adaptive equalizer. Meanwhile, a combined short convolution based parallel adaptive weight update algorithm is used to analyze the implementation structure of the weight update part of the proposed parallel adaptive equalizer. A short convolution based, effective pipelined parallel implementation structure of adaptive CMA blind equalization algorithm is then obtained, and the required relationship of pipelined delays of different modules is achieved. FPGA implementation and simulations of the proposed algorithm are also conducted, and compared with MATLAB simulation.