Design of stepping motor control IP core for array antenna successive scanning

This article uses VHDL to design a stepping motor control IP core based on FPGA which has been compiled and simulated in Quartus Ⅱ. This core calculates control parameters online, enabling every motor in the array to figure out its velocity profile and moments to send pulses in real time. At the same time, it can reduce the risk of losing steps. This IP core can handle the feedback signals from the encoder to judge and regulate step losses. The compilation result shows this IP core reduces the hardware resource consumed in real time calculation. The simulation result shows this IP core can achieve array antenna successive scanning.